In high speed digital VLSI designs, input buffers comply with the (LV) TTL interface standard, which is good enough for most applications. These input buffers are simple CMOS inverter based receivers. However, when timing becomes critical, matching between differential clocks and data signal streams are important, input signals vary in swing and common mode, such buffers are not sufficient.
State of the art receivers are complex and their design is a compromise between high speed, input offset voltage, input common-mode range, power consumption, etc.
Wide input common-mode receivers are built-on NMOS/PMOS differential (complimentary) pair with folded cascode and with a common mode feedback amplifier. Such operational amplifiers are well described in the open literature. Normally, they do not reach high speed, consume a lot of power (especial in inactive mode) and require a settling time.
On the other hand are these very fast input receivers with a reduced input common mode voltage range, e.g. simple CMOS inverters operating in push-pull fashion, self-biased CMOS receivers.
Turning to FIG. 1, illustrated is a prior art two-stage CMOS inverter based receiver. The input threshold, the output duty-cycle and the delay time changes a lot over process, supply and temperature (PVT) variations. Moreover, the duty-cycle and the delay time depend on the input signal amplitude and level. For most applications it's sufficient but moving on to higher speed, critical timings and low supply this basic stage cannot be used.